Testing semiconductor chip designs presents a formidable challenge to the chip designers. Testing in silicon is an expensive process, and thus must be reserved to the last stages of design work. Because a chip design involves millions of individual transistors, design simulation is likewise difficult, with the added issue of reliability of results, given the highly complex nature of the systems under test.
Design-For-Test (DFT) is a technique that adds testability features to a semiconductor chip. Unlike functional testing, which seeks to determine whether components perform according to their specifications, DFT seeks to determine whether the system has been configured and assembled correctly, based on the low-level building blocks set out in a system netlist. A netlist is typically a text file representation of a circuit which emphasizes the connections between the different circuit elements, perhaps independently of the physical packages constituting the actual components in the circuit. Thus, DFT assumes that the netlist is correct, and it seeks to determine whether the system has been assembled, or manufactured, according to the netlist provided. A key advantage of DFT is that is permits focusing on relatively high-level test Input/Output (I/O)'s rather than trying to access functions at the gate level, which is typically buried deep within current designs.
Conventionally, DFT methodologies include DFT synthesis followed by DFT verification, to check a synthesized design for compliance with appropriate test guidelines. During the DFT synthesis phase, test structures are inserted into the logically synthesized design, based, for example, on the netlist. Insertion of test structures into the netlist is controlled by a test descriptive file, created by the designer.
As noted above, DFT synthesis is performed by Electronic Design Automation (EDA) test tools. A number of commercially available tools, such as the Encounter Test and Diagnostic Tool, from Cadence Design Systems, and DFT Max from Synopsys, Inc., have been found suitable by those in the art for this task. The designer prepares a circuit for test by inserting test structures into a chip, which provide access points at which the designer checks for expected values of input or output. Test structures inserted into a chip during DFT synthesis are verified for compliance with test guidelines during DFT verification,
DFT synthesis and verification involve examining functional relationships involving macros, which are pre-synthesized reusable circuit blocks, which include complex circuit devices such as memory units, Phase Locked Loops (PLL) or High Speed SERDES (Serializer/Deserializer) cores (HSS Cores) etc. DFT testing for a chip including macros requires checking whether a given chip test I/O properly controls a macro I/O, a determination that in turn requires that a the path between I/Os be clearly defined, or isolated. Test I/O ports have associated attributes called test flags, and such test flags should match with test flags associated with the chip test I/O, where the chip test I/O controls the macro test I/O.
A disadvantage with the tools and methods available is that they tend to generate indistinguishable errors during DFT verification, meaning errors that cannot be characterized easily. Such disadvantages are often attributable to errors in the test descriptive file, and they produce mismatches between attributes associated with the test I/O of a macro and those associated with a chip test I/O. A further disadvantage with the available tools is that test designers/engineers are required to manually browse through the netlist using trail and error to identify errors, which is a time-consuming and cumbersome process. Moreover, available chip test tools offer no provision for checking and reporting such mismatches.
Thus, there remains a need for technology that will enable test designers to perform DFT testing that is both rapid and accurate.